Metal-oxide semiconductor field-effect transistors (FET) are a common component of integrated circuits and are typically formed by doping a Si- or Ge-based semiconductor substrate followed by deposition of several layers of semiconductor material to form a gate electrode used to control conductance through the FET. A FET can be formed as a p-type FET (pFET), having a source and a drain formed from regions doped with p-type atoms, or as a n-type FET (nFET), having a source and a drain formed from regions doped with n-type atoms. Often, pFET structures are co-fabricated with analogous nFET structures to form logic gates and other semiconductor devices. In addition to source and drain regions, FET structures are formed by depositing a layer of gate high dielectric (high k) material and a layer of conducting material (often having metal and/or highly doped polycrystalline silicon) over a semiconductor substrate with the appropriate source having drain and channel regions doped therein. In pFET structures, an electric field created by applying a negative gate-source voltage to the gate electrode causes a build up of holes to form at the boundary of high dielectric material and the transistor channel. When a sufficient voltage is applied (threshold voltage), a conductance channel is established allowing current to flow from the source to the drain. The nature of the gate material has a large effect on the threshold voltage of the transistor. A change in effective work function between the gate electrode material and the channel material as well as electrical charges in/at gate dielectric layers/interfaces can modulate the threshold voltage of a transistor.